A lot of the logic area turns out to be consumed by the shifters needed to handle the flexibility of the pin mapping options. A look at the PINCTRL register reveals four “base” selectors which implies four 32-bit barrel shifters, plus a configurable run-length tacked onto the end of the shifters. Basically, the “rotate + mask” portion of the PIO consumes more logic area than the state machine itself, and having to smash a set of rotate-masks + clock division and FIFO threshold computations into a single cycle is quite expensive time-wise. The flexibility of the PIO’s options basically means you’re emulating an FPGA-like routing network on top of an FPGA – hence the inefficiency.
林赛·戴维斯全接触：斯蒂芬·A·史密斯/2026年1月12日
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